module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);

    parameter A = 6'b000001;
    parameter B = 6'b000010;
    parameter C = 6'b000100;
    parameter D = 6'b001000;
    parameter E = 6'b010000;
    parameter F = 6'b100000;
    
    reg	[5:0]	next_state;
    
    always @(*)
        begin
            case(y)
                A:	next_state = w ? B : A;
                B:	next_state = w ? C : D;
                C:	next_state = w ? E : D;
                D:	next_state = w ? F : A;
                E:	next_state = w ? E : D;
                F:	next_state = w ? C : D;
                default:	next_state = A;
            endcase
        end
    
    assign Y1 = w&y[0];
    assign Y3 = ~w&(y[1]|y[2]|y[4]|y[5]);
    
endmodule
